vector - Shifting a 2d array in Verilog (Xilinx) -

ref : shifting 2d array verilog

my problem similar. have vector array consisting of 8 elements, each of 7 bits. have declared

wire [6 : 0][0 : 7] out_wire;     reg [6 : 0] [0 : 7] disp_data ; reg [6 : 0]  out_disp;     // output register 

now want shift each vector ,

disp_data = { out_wire[1 : 6],  out_wire[0] } ; 

and assign , in case, out_disp this

out_disp = disp_data[0] ; or disp_data[1] etc  

i using xilinx ise 14.7. everytime try synthesize, gives foll error :

expecting 'identifier', found '[' unexpected token: '[' 

i think have followed steps in reference link above. consulted reference manual. no use. i'm using verilog 2001. apologies if missed pretty basic.

relevant code here :

always @ (posedge tick_stable, posedge tick_shift) begin if (tick_shift) begin     disp_data = { out_reg[1 : 6],  out_reg[0] } ; end   else  begin     case (sel_reg)     0 :      begin         out_disp = disp_data[0] ;         enable_reg = en_z ;     end      1 :     begin         out_disp = disp_data[1] ;         enable_reg = en_f ;     end      2 :      begin         out_disp = disp_data[2] ;         enable_reg = en_s ;     end      3 :     begin         out_disp = disp_data[3] ;         enable_reg = en_t ;     end      default     begin         out_disp = 7'b1110111 ;         enable_reg = 4'b0000 ;     end     endcase   end end