Instantiation of RAM in FPGAs using VHDL -

i attempting implement dual port ram guided in this excellent blog post. however, modelsim giving following warning when compiling:

** warning: fifo_ram.vhdl(24): (vcom-1236) shared variables must of protected type. 

i seem unable create wave, indicating me variable not being recognised using code below.

how can correctly declare variable "protected" type? also, more general question shared variables - variable shared between entities in design?

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all;  entity fifo_ram      generic (data : natural := 8;              addr : natural := 16);      port (w_clk : in std_logic;           w_en : in std_logic;           w_addr : in std_logic_vector (addr-1 downto 0);           w_data : in std_logic_vector (data-1 downto 0);           --           r_clk : in std_logic;           r_rdy : in std_logic;           r_addr : in std_logic_vector (addr-1 downto 0);           r_data : out std_logic_vector (data-1 downto 0)); end fifo_ram;  architecture rtl of fifo_ram      -- shared memory     type mem_type array ( (2**addr) - 1 downto 0 ) of std_logic_vector(data-1 downto 0);     shared variable mem : mem_type;  begin     write: process (w_clk)     begin          if (rising_edge(w_clk))              if (w_en = '1')                 mem(conv_integer(w_addr)) := w_data;             end if;         end if;     end process write;  end architecture;  ----------------------------------------------  library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all;  entity tb_fifo      generic (data : natural := 8;              addr : natural := 16); end entity;  architecture testbed of tb_fifo      signal tb_w_clk, tb_w_en : std_logic := '0';     signal tb_w_addr : std_logic_vector (addr-1 downto 0);     signal tb_w_data : std_logic_vector (data-1 downto 0);     signal tb_r_clk, tb_r_rdy : std_logic := '0';     signal tb_r_addr : std_logic_vector (addr-1 downto 0);     signal tb_r_data : std_logic_vector (data-1 downto 0); begin      dut : entity work.fifo_ram(rtl)         port map(tb_w_clk, tb_w_en, tb_w_addr, tb_w_data,                  tb_r_clk, tb_r_rdy, tb_r_addr, tb_r_data);      wclock : process     begin         tb_w_clk <= '1';         wait 10 ns;         tb_w_clk <= '0';         wait 10 ns;     end process wclock;      wdata : process     begin         tb_w_addr <= x"ffff";         tb_w_data <= x"aa";         wait 100 ns;         tb_w_en <= '1';         wait 70 ns;         tb_w_en <= '0';         wait;     end process wdata;  end architecture; 

ok, having gone through blog post understand why they're using shared variable instead of signals. because multiple processes assigning variable, not possible in case of reg in verilog or signal in vhdl. in case synthesizer produce error complaining of multiple drivers mem. in order use shared variable in case, you'll have declare protected. need declare protected data type, , encapsulate mem variable inside it, classes in object oriented languages. here's example of protected data type:

type mem_envelope protected        -- protected type declaration  variable mem : mem_type;  function getval( addr : integer ) return std_logic_vector(data - 1 downto 0); function setval( addr : integer; val : std_logic_vector(data - 1 downto 0) ) return boolean; --may used indicate whether write successfull or not  end protected mem_envelope; 

then declare sharede variable of type mem_envelope , use getval , setval functions read/write values memory inside processes.